写一个软件探针

// 本站实验：Target::access
fn access(&mut self, ap: bool, read: bool, a: u8, wdata: u32) -> u32 {
  let a = a as u32;
  if !ap {
    return match (a, read) {
      (0x0, true) => 0x1BA0_1477, // DPIDR
      (0x4, true) => self.ctrl | ((self.ctrl & 0x5000_0000) << 1), // power-up ACKs mirror REQs
      // ... 写 CTRL/STAT、SELECT
      _ => 0,
    };
  }
  match ((self.select & 0xF0) | a, read) {
    (0x04, false) => { self.tar = wdata; 0 }
    (0x0C, true) => { let v = self.mem_read(self.tar & !3); self.autoinc(); v }
    (0xFC, true) => 0x2477_0011, // IDR: AHB-AP
    // ... CSW、写 DRW
    _ => 0,
  }
}

// 本站实验：Wire::swd_io 的核心
let (ap, read) = (out_bit(pos + 1), out_bit(pos + 2));
let a = ((out_bit(pos + 3) as u8) << 2) | ((out_bit(pos + 4) as u8) << 3);
let trn = pos + 8;
let wdata = (0..32).fold(0u32, |v, i| v | ((out_bit(trn + 5 + i) as u32) << i));
let data = match (ap, read, a) {
  (true, true, _) => std::mem::replace(&mut self.posted, self.target.access(true, true, a, 0)),
  (false, true, 0xC) => self.posted, // RDBUFF
  _ => self.target.access(ap, read, a, wdata),
};
let mut driven = vec![true, false, false]; // ACK = OK (0b001, LSB first)
if read {
  driven.extend((0..32).map(|i| data >> i & 1 != 0));
  driven.push(data.count_ones() % 2 == 1);
}
for (k, bit) in driven.into_iter().enumerate() {
  sampled[trn + k] = bit; // one bit early: the turnaround slot holds ACK[0]
}

// 本站实验：一个 SWD 包，8 位请求 + turnaround + 3 位 ACK + 33 位数据 + turnaround，再加 2 个空闲周期
fn packet(ap: bool, read: bool, a: u8, wdata: u32) -> Vec<IoSequenceItem> {
  use IoSequenceItem::{Input, Output};
  let (a2, a3) = (a & 4 != 0, a & 8 != 0);
  let mut v = vec![Output(true), Output(ap), Output(read), Output(a2), Output(a3)];
  v.extend([Output(ap ^ read ^ a2 ^ a3), Output(false), Output(true), Input, Input, Input, Input]);
  if read {
    v.extend(std::iter::repeat_n(Input, 34)); // 32 data + parity + turnaround
  } else {
    v.push(Input); // turnaround
    v.extend((0..32).map(|i| Output(wdata >> i & 1 != 0)));
    v.push(Output(wdata.count_ones() % 2 == 1));
  }
  v.extend([Output(false), Output(false)]); // idle
  v
}

fn mem_read(w: &mut Wire, addr: u32) -> Result<u32> {
  transfer(w, true, false, 0x4, addr)?; // TAR
  transfer(w, true, true, 0xC, 0)?; // DRW: posted, data is stale
  transfer(w, false, true, 0xC, 0) // RDBUFF
}

== part A: our own SWD host
DPIDR      = 0x1ba01477
CTRL/STAT  = 0xf0000000
    mem read  0x20000000 -> 0xcafef00d
read  0x20000000 = 0xcafef00d
    mem write 0xe000edf0 <- 0xa05f0003
    mem read  0xe000edf0 -> 0x00030003
DHCSR      = 0x00030003
    mem write 0xe000edf4 <- 0x0000000f
    mem read  0xe000edf8 -> 0x08000130
PC         = 0x08000130
## part A: 18 packets, 864 SWCLK cycles

// 本站实验
impl RawSwdIo for SoftProbe {
  fn swd_io<S>(&mut self, swdio: S) -> Result<Vec<bool>, DebugProbeError>
  where
    S: IntoIterator<Item = IoSequenceItem>,
  {
    let items: Vec<_> = swdio.into_iter().collect();
    Ok(self.wire.0.swd_io(&items))
  }
  // ... swj_pins、swd_settings
}

let mut session = Probe::new(probe).attach("STM32F103C8", Permissions::default())?;
let v = session.core(0)?.read_word_32(0x2000_0000)?;

== part B: the same target under probe-rs (RawSwdIo + polyfill)
## attach: 258 packets, 13895 SWCLK cycles
read_word_32(0x20000000) = 0xcafef00d
## read_word_32: 20 packets, 1060 SWCLK cycles
halt -> pc = 0x08000134
## halt: 44 packets, 2350 SWCLK cycles
read_core_reg(PC) = 0x08000134
## read_core_reg: 28 packets, 1490 SWCLK cycles
step -> pc = 0x08000136
## step: 64 packets, 3420 SWCLK cycles
breakpoint units = 4; set 5 breakpoints: [Ok(()), Ok(()), Ok(()), Ok(()), Err("No available hardware breakpoints")]

== part B: the same target under probe-rs (RawSwdIo + polyfill)
Error: A timeout occurred.