USART 与 DMA

        for &b in buffer {
            while !sr(r).read().txe() {}
            unsafe { tdr(r).write_volatile(b) };
        }

pub struct RingBuffer {
    #[doc(hidden)]
    pub buf: AtomicPtr<u8>,
    len: AtomicUsize,

    // start and end wrap at len*2, not at len.
    // This allows distinguishing "full" and "empty".
    // full is when start+len == end (modulo len*2)
    // empty is when start == end
    //
    // This avoids having to consider the ringbuffer "full" at len-1 instead of len.
    // The usual solution is adding a "full" flag, but that can't be made atomic
    // ...
    pub start: AtomicUsize,
    #[doc(hidden)]
    pub end: AtomicUsize,
}

unsafe fn on_interrupt(r: Regs, state: &'static State) {
    // RX
    let sr_val = sr(r).read();
    // ...
    let dr = if sr_val.rxne() || cfg!(any(usart_v1, usart_v2)) && (sr_val.ore() || sr_val.idle()) {
        Some(rdr(r).read_volatile())
    } else {
        None
    };
    clear_interrupt_flags(r, sr_val);
    // ...
    if sr_val.rxne() {
        let mut rx_writer = state.rx_buf.writer();
        let buf = rx_writer.push_slice();
        if !buf.is_empty() {
            if let Some(byte) = dr {
                buf[0] = byte;
                rx_writer.push_done(1);
            }
        } else {
            // FIXME: Should we disable any further RX interrupts when the buffer becomes full.
        }
        // ... eager_reads 或半满时 rx_waker.wake()
    }
    // ...
    if sr_val.tc() && r.cr1().read().tcie() {
        // ...
        state.tx_done.store(true, Ordering::Release);
        state.tx_waker.wake();
    }

    // TX
    if sr(r).read().txe() {
        let mut tx_reader = state.tx_buf.reader();
        let buf = tx_reader.pop_slice();
        if !buf.is_empty() {
            r.cr1().modify(|w| {
                w.set_txeie(true);
            });

            // Enable transmission complete interrupt when last byte is going to be sent out.
            if buf.len() == 1 {
                r.cr1().modify(|w| {
                    w.set_tcie(true);
                });
            }
            // ...
            tdr(r).write_volatile(buf[0].into());
            tx_reader.pop_done(1);
        } else {
            // Disable interrupt until we have something to transmit again.
            r.cr1().modify(|w| {
                w.set_txeie(false);
            });
        }
    }
}

    async fn write(&self, buf: &[u8]) -> Result<usize, Error> {
        poll_fn(move |cx| {
            let state = self.state;
            state.tx_done.store(false, Ordering::Release);

            let empty = state.tx_buf.is_empty();

            if state.tx_buf.len() < buf.len() {
                return Poll::Ready(Err(Error::BufferTooLong));
            }

            if state.tx_buf.len() - state.tx_buf.available() < buf.len() {
                return Poll::Pending;
            }

            let mut written: usize = 0;
            let mut tx_writer = unsafe { state.tx_buf.writer() };
            while written != buf.len() {
                let data = tx_writer.push_slice();
                if data.is_empty() {
                    state.tx_waker.register(cx.waker());
                    return Poll::Pending;
                }
                // ... 拷贝
            }

            if empty {
                self.info.interrupt.pend();
            }

            Poll::Ready(Ok(written))
        })
        .await
    }

unmask USART1 at 11 ms
first Ok(20), second Ok(Ok(20)) after 500 ms
40-byte write into a 32-byte buffer: Ok(Err(BufferTooLong))

unmask USART1 at 10 ms
[runq: killed after 4s]

        tx_dma: Peri<'d, D1>,
        rx_dma: Peri<'d, D2>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>>
        + interrupt::typelevel::Binding<D1::Interrupt, crate::dma::InterruptHandler<D1>>
        + interrupt::typelevel::Binding<D2::Interrupt, crate::dma::InterruptHandler<D2>>
        + 'd,

bind_interrupts!(struct Irqs {
  USART1 => usart::InterruptHandler<peripherals::USART1>;
  DMA1_CHANNEL4 => dma::InterruptHandler<peripherals::DMA1_CH4>;
  DMA1_CHANNEL5 => dma::InterruptHandler<peripherals::DMA1_CH5>;
});

error[E0277]: the trait bound `Irqs: Binding<DMA1_CHANNEL5, InterruptHandler<DMA1_CH5>>` is not satisfied
...
help: `Irqs` implements trait `Binding<I, H>`
    --> src/bin/err_dma.rs:13:1
...
     | |__`Binding<DMA1_CHANNEL4, InterruptHandler<DMA1_CH4>>`
     |    `Binding<USART1, InterruptHandler<USART1>>`

        // If we don't assign future to a variable, the data register pointer
        // is held across an await and makes the future non-Send.
        let transfer = unsafe { ch.write(buffer, tdr(r), Default::default()) };
        transfer.await;

impl<'a> Drop for Transfer<'a> {
    fn drop(&mut self) {
        self.request_reset();
        while self.is_running() {}

        // "Subsequent reads and writes cannot be moved ahead of preceding reads."
        fence(Ordering::SeqCst);
    }
}

        // make sure USART state is restored to neutral state when this future is dropped
        let on_drop = OnDrop::new(move || {
            // clear all interrupts and DMA Rx Request
            r.cr1().modify(|w| {
                // disable RXNE interrupt
                w.set_rxneie(false);
                // disable parity interrupt
                w.set_peie(false);
                // disable idle line interrupt
                w.set_idleie(false);
            });
            r.cr3().modify(|w| {
                // disable Error Interrupt: (Frame error, Noise error, Overrun error)
                w.set_eie(false);
                // disable DMA Rx Request
                w.set_dmar(false);
            });
        });

DMA write returned Ok(())

   1 DMA1: unimplemented device read  (size 4, offset 0x0a8)
   1 DMA1: unimplemented device write (size 4, offset 0x0a8, value 0x00002000)
   1 DMA1: unimplemented device write (size 4, offset 0x004, value 0x0000e000)
   1 DMA1: unimplemented device write (size 4, offset 0x04c, value 0x40013828)
   1 DMA1: unimplemented device write (size 4, offset 0x050, value 0x08003ccc)
   1 DMA1: unimplemented device write (size 4, offset 0x048, value 0x00000005)
   1 DMA1: unimplemented device write (size 4, offset 0x044, value 0x0000309a)
   1 DMA1: unimplemented device read  (size 4, offset 0x044)
   1 DMA1: unimplemented device write (size 4, offset 0x044, value 0x00000001)
   2 DMA1: unimplemented device read  (size 4, offset 0x044)
   1 DMA1: unimplemented device write (size 4, offset 0x044, value 0x0000000a)
   4 DMA1: unimplemented device read  (size 4, offset 0x044)

Trace 0: 0x700005c780 [00800408/00000000080003ec/00000010/ff031201] _RNvCs31mE9o2P3Ud_13uart_blocking18___cortex_m_rt_main
Taking exception 4 [Data Abort] on CPU 0
...at fault address 0x40013828
...with CFSR.PRECISERR and BFAR 0x40013828
...taking pending nonsecure exception 3

  [after new] ISR=0x026000c0 CR1=0x0000003d BRR=35
write_all: true
flush: false
  [after flush] ISR=0x00000000 CR1=0x0000003d BRR=35

ISR before          0x026000c0
ICR = TCCF       -> 0x02600080
ICR = old ISR    -> 0x00000000

write Ok(())
isr 0x26000c0 cr1 0xd

  [after new] ISR=0x026000c0 CR1=0x0000003d BRR=35
hello from BufferedUart
write_all: true
flush: true
  [after flush] ISR=0x02600080 CR1=0x0000003d BRR=35
read: true Ok("abcde")

        let mut bus = self.bus.lock().await;
        self.cs.set_low().map_err(SpiDeviceError::Cs)?;

        let cs_drop = OnDrop::new(|| {
            // This drop guard deasserts CS pin if the async operation is cancelled.
            // Errors are ignored in this drop handler, as there's nothing we can do about them.
            // If the async operation is completed without cancellation, this handler will not
            // be run, and the CS pin will be deasserted with proper error handling.
            let _ = self.cs.set_high();
        });

blocking_write returned Ok(())

$ wc -c serial-dmab.txt serial-dma.txt
       5 serial-dmab.txt
       0 serial-dma.txt
       5 total